1. Field of the Invention
Embodiments of the present invention generally relate to the design of voltage regulators. More specifically, embodiments of the present invention provide a low-voltage regulator with ripple compensation.
2. Related Art
Modern high-speed circuits are increasingly requiring voltage regulators that can generate a stable output voltage using low supply voltages. For example, universal serial bus (USB) circuits, peripheral component interface express (PCIe) circuits, and other such high-speed circuits can require output voltages of 1.2 V to be generated from supply voltages of 1.8 V or lower. Unfortunately, as the output voltages required for these circuits are remaining approximately constant, the supply voltages available to the voltage regulators are being scaled downward much more aggressively. Because the difference between the output voltages required to be output by the regulator and the supply voltages that are provided to voltage regulator is decreasing, circuit designers have struggled to design voltage regulators that are simple and reliable and do not require excessive area or power. This issue is generally referred to as a headroom problem.
One proposed voltage regulator uses an NMOS transistor as part of a voltage-regulation element. For example, FIG. 1A presents a circuit diagram illustrating such an NMOS voltage regulator. Note that NMOS voltage regulators provide low output impedance at high frequency and require less area than other voltage regulator designs. However, NMOS voltage regulators require a high supply voltage on node VDD to ensure that the voltage regulator is able to maintain the NMOS transistor in the “on” state. Specifically, the node VGATE needs to be at least a threshold voltage above the node VREG to maintain the NMOS transistor in the “on” state (where the threshold voltage is approximately 1 V due to the body effect). Consequently, as supply voltages shrink, NMOS voltage regulators may no longer be able to properly regulate the output voltage on the output node VREG.
Another proposed voltage regulator uses a PMOS transistor as part of a voltage-regulation element. For example, FIG. 1B presents a circuit diagram illustrating such a PMOS voltage regulator. PMOS voltage regulators do not require as high a supply voltage on node VDD as the NMOS voltage regulator. This is because the node VGATE in a PMOS voltage regulator only needs to be at least a threshold voltage below the node VDD to maintain the PMOS transistor in the “on” state. However, PMOS voltage regulators have a high output impedance beyond the operational amplifier's bandwidth, which can cause a “ripple” in the output voltage on the output node VREG when the voltage regulator is used in high-speed transient switching circuits.
For example, FIG. 1C presents a graph illustrating ripple in the output voltage on the output node VREG of a PMOS voltage regulator during a series of high-speed logical transitions in an integrated circuit that uses the VREG node as a power supply. To reduce such ripples in the output voltage, PMOS voltage regulators typically include a capacitor coupled to the output node VREG. FIG. 1D presents a circuit diagram of a PMOS voltage regulator that includes such a capacitor (CBIG) on the output node VREG. Unfortunately, adding capacitance to the output node has drawbacks, such as requiring additional area and creating stability problems.